Intel reveals details of six core Xeon CPUs

Intel has confirmed details of its forthcoming six-core and Itanium chips, which are expected to ship in the second half of this year.

The new six-core processor, codenamed Dunnington, will be based on Intel's 45nm Penryn processor and will be socket compatible with the current Caneland platform, introduced last year and already used by most manufacturers of industry-standard servers.

This will increase the maximum cores amount of cores in the platform to go from 16 to 24. In addition, the cores will support up to 16MB of level 3 cache. FlexMigration will also be a key feature of Dunnington, enabling virtual machine workloads to be transferred between processors independent of micro architecture - another industry first, according to the chip maker.

The new Itanium processor, designed for mission-critical server applications and codenamed Tukwila, is quad-core processor design with two billion transistors. This is the most any manufacturer has placed on a CPU to date.

Built on 65nm manufacturing process, Tukwila will have a massive 30MB cache and employ multi-threaded technology, making it capable of operating on two threads per core or up to eight threads in parallel.

The chip will employ QuickPath interconnect technology, Intel's equivalent to AMD's HyperTransport, to supply data to its dual integrated memory controllers. It will operate at clock speeds of up to 2GHz and Intel claims that the processor will offer up to twice the performance of the current generation, Itanium 9100 series processor.

Steve Smith, vice president and director of Intel's Digital Enterprise Group Operations, said that the processor "had been built from the ground up at circuit level with RAS (Reliability, Availability, and Serviceability) features." He confirmed that the chip was also expected to be in production later this year.

Finally, Intel provided details of its new Nehalem micro-architecture, designed to replace its current Core 2 Duo line for the desktop. This will scale from two up to eight cores, but Intel confirmed that it will launch with only four and will arrive before the end of the year. It will be paired with the Tylersburg chipset.

Nehalem is significant for Intel as it moves away from its traditional front-side bus architecture to one with an integrated memory controller, a design that AMD introduced in 2003.

Citing its bandwidth latency enhancements, Ronak Singhal, principal engineer, Digital Enterprise Group said that Nehalem was Intel's, "most scalable and most dynamic design ever".

Email to a friend

Print this page

Social Bookmark this article: What is this?

Digg

Delicious

Reddit

StumbleUpon

Slashdot

Google

Facebook