IDF: Intel talks up next-gen chips

gallery

Dunnington, Tukwila, Nehalem and Larrabee processors were the talk of the Intel Developer Forum keynote from Patrick Gelsinger, Intel's senior vice president and Digital Enterprise Group general manager in Shanghai earlier today.

In a podcast to preview his keynote, he said Intel was "taking our architecture and extending it from the very big to the very, very small with low power".

But, while news that mobile internet devices (MID) will soon ship with Intel's Atom microprocessor technology dominated the opening day of the annual event, Gelsinger talked up his "milliwatts to petaflops" processor plans.

Intel's first six-core Xeon 'Dunnington' chip was demonstrated for its ability to handle VMware migrations on the fly. Designed for expandable multi-processor servers, with Intel's current 7300 chipset-based platform, combined with its quad-core Xeon 7300 processor and socket-compatible with its Caneland platform, used by most industry standard servers, it will ship in the second half of 2008.

And the FlexMigration technology highlighted in Dunnington allows for one compatible server virtualisation pool that supports live virtual machine migration across both 65nm and 45nm Intel Core micro-architecture based servers and 45nm-based servers.

Attendees at the show reported the Tukwila demonstration had problems running a high-performance computational fluid dynamics (CFD) package. But it was touted as "the world's first two billion transistor microprocessor" that is projected to deliver more than double the performance of the current generation Itanium processor for mainframe-class performance. Specifications will include four cores, 30MB total cache, dual Integrated Memory Controller and QuickPath Interconnect.

Intel confirmed its new processor micro-architecture, Nehalem will start production in the fourth quarter of 2008 and deliver" four times the memory bandwidth compared to today's highest-performance Intel Xeon processor-based systems". Future versions will scale from two to eight cores, with simultaneous multi-threading, enabling four- to 16-thread capability.

And Gelsinger reckoned with up to 8MB level-3 cache, 731 million transistors, Quickpath interconnects (up to speeds of 25.6GB per second), integrated memory controller and optional integrated graphics, Nehalem will eventually scale from notebooks to high-performance servers.

With plans for the first demonstrations later this year, he also said the Larrabee programmable processing architecture will be next step in evolving the visual computing platform. It includes a high-performance, parallel vector processing unit (VPU) along with a new set of vector instructions including integer and floating point arithmetic, vector memory operations and conditional instructions to support advanced graphics software development.

Gelsinger added that Larrabee includes a new hardware coherent cache design to enable its many-core architecture, while its products are being designed to support industry application programming interfaces (APIs) such as DirectX and OpenGL.

Email to a friend

Print this page