Intel Outlines a terascale future

Intel used its Intel Developer Forum event in San Francisco to display the three pillars of its terascale processor vision: teraflop processor performance, with terabyte per second memory bandwidth and terabit I/O - and to show off silicon that should deliver that vision.

Justin Rattner, Intel's chief technical officer, described it as a response to increasing demand by consumers and businesses for Internet-based software, services and media-rich experiences, and a shift to hosted personal data, media and applications, accessed by high-performance devices. It's a usage model that will require one trillion floating-point operations-per-second (teraFLOPs) of performance and terabytes of bandwidth.

Rattner said, "Solving these challenges will bring benefits to all computing devices while creating new markets and opportunities for developers and systems designers."

He used his keynote speech to unveil terascale research prototype silicon, in the shape of what Intel is calling the world's first programmable TeraFLOP processor. With 80 simple cores on a single die, and operating at 3.1 GHz, the chip has been designed to test how processors can move terabytes of data from core to core and between cores and memory.

Using a simple floating point instruction set, and an onboard router, each core is linked into an on-chip network. The cores are also directly connected to a stacked 20 megabyte SRAM chip, with over a terabyte per second bandwidth between the memory and the processor cores. Intel is expecting to use derivatives of these experimental processors along with its recently announced silicon laser technology. The teraflop processors will use silicon lasers as terabit-speed device interconnects.

Commercial applications are still some time away, according to Rattner, "While any commercial application of these technologies is years away, it is an exciting first step in bringing tera-scale performance to PCs and servers."

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