IBM doubles chip performance, triples processor memory
New IBM technology breakthrough could improve chip performance by putting eDRAM memory on processors.
Described as a 'first of its kind' for eDRAM (embedded dynamic random access memory), the technology was designed to a 65nm process, but is expected to fit into IBM's 45nm chip roadmap for commercial manufacture.
IBM says the technology offers high-performance at lower power, using just 20 per cent of the standby power drawn by conventional SRAM memory (static random access memory), and is physically a third of the size.
'With this breakthrough solution to the processor/memory gap, IBM is effectively doubling microprocessor performance beyond what classical scaling alone can achieve,' said Dr. Subramanian Iyer, Distinguished Engineer and director of 45nm technology development at IBM. 'As semiconductor components have reached the atomic scale, design innovation at the chip-level has replaced materials science as a key factor in continuing Moore's Law. Today's announcement further demonstrates IBM's leadership in this critical area of microprocessor design innovation.'
The on-chip memory specification includes random cycle times of 2 nano second, with a latency of 1.5 nano seconds. Each cell measures 0.126 mm2 and draws 42 mW on standby, and 76 mW otherwise.
Multi-core chips in particular should benefit from the new memory technology, which will improve graphics performance for multimedia applications and games, said IBM.
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